View ST8008_4538482.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ST
ST8008
PRELIMINARY Notice: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. specification. Some parameters are subject to change.
80 Output LCD Segment Driver IC
This is not a final
DESCRIPTION
The ST8008 is a 80-output segment driver IC suitable for driving small/medium scale dot matrix LCD panels, and is used in PDA or electronic dictionary. The ST8008 is good as a segment driver, and it can create a low power consuming, high-resolution LCD.
FEATURES
Number of LCD drive outputs: 80 Supply voltage for LCD drive: Max +16V Supply voltage for the logic system: +2.5 to +5.5 V Low power consumption Package: 96-pin COB. (Segment mode) Shift clock frequency - 20 MHz (MAX.): VDD = +5.0 0.5 V - 15 MHz (MAX.): VDD = +3.0 to + 4.5 V - 12 MHz (MAX.): VDD = +2.5 to + 3.0 V Adopts a data bus system 4-bit parallel / serial input modes are selectable with a mode (P/S) pin Automatic transfer function of an enable signal Automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 80 bits of input data Line latch circuits are reset when XDISPOFF active
V0.3
1/ 21
2004/04/05
PIN1
37 36 35 34 33 32 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 24 7
6
5
4
3
2
1
SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21
38 39 40 41 42 43 44 45 46 47 48 49
97
96
93
89
88
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Chip size: 3800(m)X1560(m)
Pad Arrangement
Substrate Connect to Vss.
Pad size: 80(m)X80(m) Pin Pitch: 100(m)~120(m)
Origin: chip center(0,0)
Chip Thiclness:19 mil
V0.3
2/21
92
SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58
2004/04/05
ST8008
ST8008
Pad Location Coordinates
Pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Function CS[70] CS[71] CS[72] CS[73] CS[74] CS[75] CS[76] CS[77] CS[78] CS[79] V0 V2 V3 ED[3] ED[2] ED[1] ED[0] EIO1 EIO2 XCKPAD FRPAD LPPAD VDD LRPAD XDISPAD PSPAD VSS CS[0] CS[1] CS[2] CS[3] CS[4] CS[5] CS[6] CS[7] CS[8] X 1785 1665 1555 1450 1350 1250 1150 1050 950 850 750 650 550 450 350 250 150 50 -50 -150 -250 -350 -450 -450 -550 -650 -750 -850 -950 -1050 -1150 -1250 -1350 -1450 -1555 -1665 Y 665 665 665 665 665 665 665 665 665 665 665 665 665 665 665 665 665 665 665 665 665 665 665 517.15 665 665 665 665 665 665 665 665 665 665 665 665 Pad No 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Function CS[9] CS[10] CS[11] CS[12] CS[13] CS[14] CS[15] CS[16] CS[17] CS[18] CS[19] CS[20] CS[21] CS[22] CS[23] CS[24] CS[25] CS[26] CS[27] CS[28] CS[29] CS[30] CS[31] CS[32] CS[33] CS[34] CS[35] CS[36] CS[37] CS[38] CS[39] CS[40] CS[41] CS[42] CS[43] CS[44] X -1785 -1785 -1785 -1785 -1785 -1785 -1785 -1785 -1785 -1785 -1785 -1785 -1785 -1785 -1665 -1555 -1450 -1350 -1250 -1150 -1050 -950 -850 -750 -650 -550 -450 -350 -250 -150 -50 50 150 250 350 450 Y 665 555 450 350 250 150 50 -50 -150 -250 -350 -450 -555 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665
V0.3
3/21
2004/04/05
ST8008
Pad No 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97
Function CS[45] CS[46] CS[47] CS[48] CS[49] CS[50] CS[51] CS[52] CS[53] CS[54] CS[55] CS[56] CS[57] CS[58] CS[59] CS[60] CS[61] CS[62] CS[63] CS[64] CS[65] CS[66] CS[67] CS[68] CS[69]
X 550 650 750 850 950 1050 1150 1250 1350 1450 1555 1665 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785
Y -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -665 -555 -450 -350 -250 -150 -50 50 150 250 350 450 555
V0.3
4/21
2004/04/05
ST8008
PIN DESCRIPTION
SYMBOL SEG0-SEG79 V0,V2,V3 XDISPOFF VDD EIO2, EIO1 DI0-DI3 XCK L/R LP FR I/O O P I P I/O I I I I LCD drive output Power supply for LCD drive Control input for output of non-select level Power supply for logic system (+2.5 to +5.5 V) Input/output for chip selection at segment mode and FLM input output function at com/seg mix mode or common mode Display data input at segment mode Clock input for taking display data at segment mode Display data shift direction selection Latch pulse input for display data at segment mode/ Shift clock input for shift register at common mode I AC-converting signal input for LCD drive waveform This is the parallel data input/serial data input switch terminal. P/S I P/S="H": Parallel data input. P/S="L": Serial data input. VSS P Ground (0 V) 1 1 1 1 DESCRIPTION No of Num 80 3 1 1 2 4 1
V0.3
5/21
2004/04/05
ST8008
BLOCK DIAGRAM
V0.3
6/21
2004/04/05
ST8008
INPUT/OUTPUT CIRCUITS
V DD
I
T o In te rn a l C irc u it A p p lic a b le P in s X D IS P O F F , D I3~ D I0 , L P , F R , P /S ,L /R
V s s (0 V )
Input Circuit
V
DD
I /O
To Internal Circuit Control Signal
Vss (0V)
Vss (0V)
V DD
Output Signal
Application Pins EIO Control Signal Vss (0V)
1
, EIO
2
Input/Output Circuit
V0.3
7/21
2004/04/05
ST8008
FUNCTIONAL DESCRIPTION
Pin Functions
SYMBOL VDD VSS FUNCTION Logic system power supply pin, connected to +2.5 to +5.5 V. Ground pin, connected to 0 V. This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or V0 V2 V3 through changing the impedance using an op. amp. Voltage levels are determined based on VSS, and must maintain the relative magnitudes shown below. V0 V2 V3Vss Input pins for display data In 4-bit parallel input mode, input data into the 4 pins, DI3-DI0. DI3-DI0 In serial input mode, input data into the 1 pin DI0. Connect DI3-DI1 to VSS or VDD Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. XCK Clock input pin for taking display data * Data is read at the falling edge of the clock pulse. Latch pulse input pin for display data Data is latched at the falling edge of the clock pulse. Control input pin for output of non-select level The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to VSS level "L", the LCD drive output pins (SEG0~SEG79) are set to level Vss. XDISPOFF When set to "L", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of /DISPOFF. When the XDISPOFF function is canceled, the driver outputs non-select level (V2 or V3), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if XDISPOFF removal time does not correspond to what is shown in AC characteristics, it cannot output the reading data correctly. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. FR Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. P/S Interface Mode selection pin When P/S is "H" then parallel data input mode.
LP
V0.3
8/21
2004/04/05
ST8008 When P/S is "L" the serial data input mode, Input pin for selecting the reading direction of display data. Default value is LOW When set to VSS level "L", data is read sequentially from SEG79 to SEG0. L/R When set to VDD level "H", data is read sequentially from SEG0 to SEG79. Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Input/output pins for chip selection. AT segment mode: When L/R input is at VSS level "L", ElO1 is set for output, and EIO2 is set for input(connect to Vss). When L/R input is at VDD level "H", ElO1 is set for input(connect to Vss), and EIO2 is set for ElO1, EIO2 output. During output, set to "H" while LP * XCK is "H" and after 80 bits of data have been read, set to "L" for one cycle (from falling edge to failing edge of XCK), after which it returns to "H". During input, the chip is selected while El is set to "L" after the LP signal is input. The chip is non-selected after 80 bits of data have been read. LCD drive output pins SEG0-SEG79 Corresponding directly to each bit of the data latch, one level (V0, V2, V3, and Vss) is selected and output. Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
Functional Operations
FR L L H H X LATCH DATA L H L H X /DISPOFF H H H H L TRUTH TABLE NOTES: L : VSS (0 V), H : VDD (+2.5 to +5.5 V), "Don't care" should be fixed to "H" or "L", avoiding floating. There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver. Supply regular voltage that is assigned by specification for each power pin. LCD DRIVE OUTPUT VOLTAGE LEVEL (SEG0-SEG79) V3 Vss V2 V0 Vss
V0.3
9/21
2004/04/05
ST8008
RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS (A) 4-bit Parallel Input Mode
DATA NUMBER OF CLOCKS
L/R
EIO1
EIO2
INPUT 20 CLOCK 19 CLOCK 18 CLOCK ... 3 CLOCK 2 CLOCK 1 CLOCK DI0 SEG0 SEG1 SEG2 SEG3 SEG79 SEG78 SEG77 SEG76 SEG4 SEG5 SEG6 SEG7 SEG75 SEG74 SEG73 SEG72 SEG8 SEG9 SEG10 SEG11 SEG71 SEG70 SEG69 SEG68 ... ... ... ... ... ... ... ... SEG68 SEG69 SEG70 SEG71 SEG11 SEG10 SEG9 SEG8 SEG72 SEG73 SEG74 SEG75 SEG7 SEG6 SEG5 SEG4 SEG76 SEG77 SEG78 SEG79 SEG3 SEG2 SEG1 SEG0
L
Output Input
Dl1 DI2 DI3 DI0
H
Input
Output
Dl1 DI2 DI3
(B) Serial Input Mode
DATA NUMBER OF CLOCKS 3 CLOCK SEG77 X X X SEG2 X X X 2 CLOCK SEG78 X X X SEG1 X X X 1 CLOCK SEG79 X X X SEG0 X X X
L/R EIO1
EIO2
INPUT 80 CLOCK 79 CLOCK 78 CLOCK ... DI0 SEG0 X X X SEG79 X X X SEG1 X X X SEG78 X X X SEG2 X X X SEG77 X X X ... X X X ... X X X
L Output Input
Dl1 DI2 DI3 DI0
H
Input Output
Dl1 DI2 DI3
NOTES: L : VSS (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care "Don't care" should be fixed to "H" or "L", avoiding floating.
V0.3
10/21
2004/04/05
ST8008
Connection examples of plural segment drivers
(A) When L/R = "L"
Top data Data flow Last data
SEG79
EIO2
SEG0
EIO1 L/R
SEG79
EIO2
SEG0 SEG79
EIO1 L/R EIO2
SEG0
EIO1 L/R
DI3-DI0
DI3-DI0
DI3-DI0
XCK
XCK
XCK
FR
FR
FR
LP
LP
LP
XCK LP
FR DI3-DI0 4
VSS
(B)
When L/R = "H"
VDD
XCK LP
FR DI3-DI0 4
L/R Vss EIO1 EIO2
XCK
LP
FR
DI3-DI0
L/R EIO1 EIO2
XCK
LP
FR
DI3-DI0
L/R EIO1 EIO2
XCK
LP
FR
SEG0
Top data
SEG79
Data flow
SEG0 SEG0 SEG79
SEG79
Last data
DI3-DI0
V0.3
11/21
2004/04/05
ST8008 Timing chart of 4-device cascade connection of segment drivers
FR
LP
XCK
TOP DATA DI3 - DI0 n* 1 2 n* 1 2 n* 1 2 n* 1 2 n* 1
LAST DATA 2
device A
device B
device C
device D
EI (device A)
EO (device A)
EO (device B)
EO (device C)
*n = 20 in 4-bit parallel input mode *n = 80 in serial input mode
V0.3
12/21
2004/04/05
ST8008
PRECAUTIONS
Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so a high current that may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating may permanently damage it. The details are as follows, When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on XDISPOFF function. After that, cancel the XDISPOFF function after the LCD drive power supply has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to level Vss on XDISPOFF function. Then disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, follow the recommended sequence shown here
VDD VDD VSS
VDD XDISPOFF VSS
VDD V0 VSS
V0.3
13/21
2004/04/05
ST8008
Application Timing Block: Example 160X80 Frame and Lp falling edge (or rising edge) must >10ns
Parallel vs. Serial Interface Diagram
S1 S2 S3 S4 S5 S6 S7 S8 S15 7 1 2 3 4 5 6 7 8 157 158 S158 S15 9 159 S16 0 160
LP
D3 D2 D1 D0
1 2 3 4
5 6 7 8
9 10 11 12
13 14 15 16
145 146 147 148
149 150 151 152
153 154 155 156
157 158 159 160
1 2 3 4
5 6 7 8
9 10 11 12
D0
1
2
3
4
5
6
7
8
157
158
159
160
V0.3
14/21
2004/04/05
ST8008
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage (1) SYMBOL VDD V2 V3 Input voltage Storage temperature NOTES: 1. TA = +25 C 2. The maximum applicable voltage on any pin with respect to VSS (0 V). VI TSTG APPLICABLE PINS VDD V2 V3 D14-DI0, XCK, LP, L/R, FR, EIO1, EIO2, XDISPOFF RATING UNIT V NOTE
-0.3~+7.0
VDD-10~ VDD+0.3 -0.3~V5S+10
V V C
1,2
-0.3 to VDD+0.3
-45 to +125
RECOMMENDED OPERATING Conditions
PARAMETER Supply voltage (1) Supply voltage (2) Operating temperature NOTES: 1. The applicable voltage on any pin with respect to VSS (0 V). 2. Ensure that voltages are set such that V2 V3 VSS. SYMBOL VDD V0 TOPR APPLICABLE PINS VDD V0 MIN. +2.5 +6.0 -20 TYP. MAX. +5.5 +16.0 +85 UNIT NOTE V V C 1, 2
V0.3
15/21
2004/04/05
ST8008
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = + 6.0 to +15.0 V, TOPR = -20 to +85C) PARAMETER Input "Low" voltage SYMBOL VIL CONDITIONS APPLICABLE PINS DI3-DI0, XCK, LP, L/R FR, EIO1, EIO2, Input "High" voltage Output "Low" voltage Output "High" voltage VIH VOL VOH ILIL Input leakage current ILIH VI = VDD |VON| V0 = 30 =0.5V V IOL = +0.4 mA IOH = -0.4 mA VI = VSS DI3-DI0, XCK, LP, LIR, FR, EIO1, EIO2, XDISPOFF SEG0-SEG79 VSS VSS V0 1.5 XDISPOFF EIO1, EIO2 VDD-0.4 -10 +10 0.8VDD +0.4 MIN. TYP. MAX. UNIT NOTE 0.2VD D V V V A A V
Output resistance Standby current Supply current (1) (Non-selection) Supply current (2)
RON ISTB ISS I0
2.0 50 2.0 0.9
k A mA mA 1 2 4
NOTES: 1. VDD = +3.0 V, V0 = +12.0 V 2. VDD = +3.0 V, V0 = +12.0 V, fXCK = 8 MHz, no-load, El = VDD. The input data is turned over by data taking clock (4-bit parallel input mode). 3. VDD = +3.0 V, V0 = +12.0 V, fXCK = 8 MHz, no-load, El = VSS. The input data is turned over by data taking clock (4-bit parallel input mode). 4. VDD = +3.0 V, V0 = +12.0 V, fXCK = 8MHz, fLP = 19.2 kHz, fFR = 80 Hz, no-load. The input data is turned over by data taking clock (4-bit parallel input mode).
V0.3
16/21
2004/04/05
ST8008
AC Characteristics
(VSS = 0 V, VDD = +2.5 to +3.0 V, V0 = + 6.0 to +15.0 V, TOPR = -20 10+85 C) PARAMETER SYMBOL CONDITIONS MIN TYP. Shift clock period tWCK tR,tF 11ns 125 Shift clock "H" pulse width tWCKH 51 Shift clock "L" pulse width tWCKL 51 Data setup time tDS 30 Data hold time tDH 40 Latch pulse "H" pulse width tWLPH 51 Shift clock rise to latch pulse rise time tLD 0 Shift clock fall to latch pulse fall time tSL 51 Latch pulse rise to shift clock rise time tLS 51 Latch pulse fall to shift clock fall time tLH 51 Latch pulse fall to shift clock rise time tLSW 50 Enable setup time tS 36 Input signal rise time tR Input signal fall time tF DISPOFF removal time tSD 100 DISPOFF "L" pulse width tWDL 1.2 Output delay time (1) tD CL = 15 pF Output delay time (2) tPD1, t PD2 CL = 15 pF Output delay time (3) t PD3 CL = 15 pF NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. (VSS = 0 V, VDD = +5.00.5 V, V0 = + 6.0 to +15.0 V, TOPR = -20 to +85 C) PARAMETER SYMBOL CONDITIONS Shift clock period tWCK tR,tF 10ns Shift clock "H" pulse width tWCKH Shift clock "L" pulse width tWCKL Data setup time tDS Data hold time tDH Latch pulse "H" pulse width tWLPH Shift clock rise to latch pulse rise time tLD Shift clock fall to latch pulse fall time tSL Latch pulse rise to shift clock rise time tLS Latch pulse fall to shift clock fall time tLH Latch pulse fall to shift clock rise time tLSW Enable setup time tS Input signal rise time tR Input signal fall time tF DISPOFF removal time tSD DISPOFF "L" pulse width tWDL Output delay time (1) tD CL = 15 pF Output delay time (2) tPD1, tPD2 CL = 15 pF Output delay time (3) tPD3 CL = 15 pF NOTES:1. Takes the cascade connection into consideration. MIN. 66 23 23 15 23 30 0 50 30 30 50 15 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s NOTE 1 MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s NOTE 1
50 50
2 2
78 1.2 1.2
50 50 100 1.2 41 1.2 1.2
2 2
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
V0.3
17/21
2004/04/05
ST8008 (VSS = 0 V, VDD = +3.0 to +4.5 V, V0 = + 6.0 to +15.0 V, TOPR = -20 10+85 C) PARAMETER SYMBOL CONDITIONS Shift clock period tWCK tR,tF 10ns Shift clock "H" pulse width tWCKH Shift clock "L" pulse width tWCKL Data setup time tDS Data hold time tDH Latch pulse "H" pulse width tWLPH Shift clock rise to latch pulse rise time tLD Shift clock fall to latch pulse fall time tSL Latch pulse rise to shift clock rise time tLS Latch pulse fall to shift clock fall time tLH Latch pulse fall to shift clock rise time tLSW Enable setup time tS Input signal rise time tR Input signal fall time tF DISPOFF removal time tSD DISPOFF "L" pulse width tWDL Output delay time (1) tD CL = 15 pF Output delay time (2) tPD1, t PD2 CL = 15 pF Output delay time (3) t PD3 CL = 15 pF NOTES:1. Takes the cascade connection into consideration. MIN. 82 28 28 20 23 30 0 51 30 30 50 15 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s NOTE 1
50 50 100 1.2 57 1.2 1.2
2 2
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
V0.3
18/21
2004/04/05
ST8008
Timing Chart of Segment Mode
tWLPH
LP
tLD tLS tSL tLH tWCKH tWCKL
XCK
tR tWCK tF tDS tDH
DI4 - DI0
LAST DATA
TOP DATA
tWDL
tSD
XDISPOFF
FR tPD1 LP tPD2 XDISPOFF tPD3 SEG0 - SEG79
V0.3
19/21
2004/04/05
ST8008
Application Circuit (a) When use one ST8009 and two ST8008 (160X96)
(b) When use one ST8009 and one ST8008 (112X64)
V0.3
20/21
2004/04/05
ST8008
ST8008 Serial Specification Revision History ST8008 Serial Specification Revision History Version 0.0 0.1 0.2 0.3 Date 2004/01/05 2004/04/05 2004/09/08 2005/02/14 Description Preliminary version Add application timing block diagram Define timing of segment mode . Revise graph of ST8008(SID, SCLK)
The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without permission from Sitronix.
V0.3
21/21
2004/04/05

▲Up To Search▲

Price & Availability of ST8008

	To Download ST8008 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .